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JTAG-Booster for Analog Devices ADSP-21xxx
FLAG10 Inp
FLAG11 Inp
PWM_EVENT1 Inp
PWM_EVENT0 Inp
SDCLK1 Out,Lo
// Flag Pin
// Flag Pin
// PWM output/event capture
// PWM output/event capture
// SDRAM clock output
// The direction of each following pin can be set independent of the others,
// but this pins can not be read back.
REDY Inp // Host Bus Acknowledge
DT0_A Out,Lo // Data Transmit
DT0_B Out,Lo // Data Transmit
DT1_A Out,Lo // Data Transmit
DT1_B Out,Lo // Data Transmit
EMU# Inp // Emulation Status
// The following pin has an open drain output with a weak pull up.
// The pin is bidirectional.
CPA# Inp // Core Priority Access
// The following pins are output only pins.
// Setting to input (tristate) one of these pins results in an error.
BMSTR Out,Hi // Bus Master Output
// The following pins are input only.
// Setting to output of one of these pins results in an error.
// Declaration of the direction of these pins is optional.
IRQ0# Inp // Interrupt Request
IRQ1# Inp // Interrupt Request
IRQ2# Inp // Interrupt Request
BSEL Inp // EPROM Boot Select, BSEL=1 -> Boot from EPROM
RESET# Inp // Processor Reset
ID0 Inp // Multiprocessing ID
ID1 Inp // Multiprocessing ID
CLKIN Inp // Clock In
CS# Inp // Chip Select Input
DR0_A Inp // Data Receive
DR0_B Inp // Data Receive
DR1_A Inp // Data Receive
DR1_B Inp // Data Receive
HBR# Inp // Host Bus Request
DMAR1# Inp // DMA Request 1, DMA Channel 7
DMAR2# Inp // DMA Request 2, DMA Channel 8
SBTS# Inp // Suspend Bus Three-State
JTAG_ADSP-21xxxa.doc
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